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Verification Techniques for System-Level Design:
Material type:
TextLanguage: English Publication details: Amsterdam Boston Morgan Kaufmann Publishers 2008Description: 240ISBN: - 9780123706164 (pbk.)
- 0123706165 (pbk.)
- 621.3815Â MUK/V
| Item type | Current library | Collection | Call number | Status | Barcode | |
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Books
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Indian Institute of Technology Tirupati General Stacks | Computer Science | 621.3815 MUK/V (Browse shelf(Opens below)) | Available | 07185 | |
Reference
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Indian Institute of Technology Tirupati Reference | Computer Science | REF 621.3815 FujV (Browse shelf(Opens below)) | Not for loan | 07186 |
Browsing Indian Institute of Technology Tirupati shelves, Shelving location: Reference, Collection: Computer Science Close shelf browser (Hides shelf browser)
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| REF 620.0015194 ChaN6 Numerical Methods : for Engineers [6th ed.] / | REF 620.00285 RicN2 Numerical Methods, Software and Analysis | REF 620.002855369 EttE Engineering Problem Solving with C | REF 621.3815 FujV Verification Techniques for System-Level Design: | REF 621.392 BhaV A VHDL Primer | REF 621.392 PalV2 Verilog Hdl : A Guide to Digital Design And Synthesis [2nd ed.] / | REF 621.392 RotD2 Digital Systems Design Using VHDL/ |
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