000 nam a22 7a 4500
999 _c2528
_d2528
005 20180320164132.0
008 180320b xxu||||| |||| 00| 0 eng d
020 _a9783319025469
041 _aeng
082 _a005.71
_bEDU
100 _aEDUARDO AUGUSTO BEZERRA
245 _aSYNTHESIZABLE VHDL DESIGN FOR FPGAs
260 _aSWITZERLAND
_bSPRINGER
_c2014
300 _a157
700 _aDJONES VINICIUS LETTNIN
942 _cBK